Modern semiconductor devices can employ hundreds of thousands of gates, and more than a million individual transistors. Aside from the design challenges, discussed briefly below, physical devices must be rigorously tested to verify not only correct functionality but also failure-free fabrication. A common fabrication problem is metallization failure.
Metallization failures in integrated circuits are mostly caused by corrosion, mechanical stress and electromigration. These failures are described in Failure Mechanisms in Semiconductor Devices, Amerasekera and Campbell, John Wiley & Sons, 1987, pp. 35-45.
Various diagnostic "tools" have been used individually to locate, confirm and analyze failures in complex integrated circuits. These tools include:
a. Liquid Crystal techniques, wherein a liquid crystal material is "painted" onto a powered-up device, are useful in mapping the general location of a defect, which will exhibit itself (by color change) as "leakage site" on the device. However, these techniques are not useful in accurately pinpointing the defect site, due to poor resolution.
b. Micro-probing techniques, wherein a probe is physically placed on the device, such as at a particular metal trace, is useful in pinpointing a failure, which will exhibit itself as a voltage on the probe. However, such physical probing techniques tend to be destructive, and are limited to technologies greater than one micron. They simply are not feasible for devices employing submicron technologies.
c. Photo-emission microscopy can detect power dissipation in transistors, and is based on the principle of detecting photons generated during electron-hole pair recombination, and has been used to detect leakages typically in the nano-Amp (nA) to milliAmp (mA) range, such as from gate-oxide leakage, junction spiking and latch-up phenomena, electrostatic discharge (ESD) induced failures, avalanche breakdown, and transistors operating in saturation. It is however ineffective in detecting resistive shorts, since very little, if any, electron-hole pair recombination occurs at these sites. Thus, failures such as heavily damaged dielectrics and junctions would not be able to be detected. Furthermore, photo-emission testing is sensitive to the transistor type, and has a greater chance of detecting n-channel than p-channel MOS (Metal Oxide Semiconductor) defects.
d. E-Beam (Electron Beam) voltage contrast microscopy is based on the principle that a focussed beam of electrons can be used to measure the voltage waveform on the metallization of a VLSI circuit, and has been used to detect failing circuit functionality, namely open metal, open contact and open via. The focussed primary electron beam is directed onto the region of interest, and low energy electrons are produced through secondary emission. A Scintillator/Photomultiplier is used to detect the voltage on the metallization of the VLSI chip. Defects are identifiable regardless of the magnitude of the leakage current. An example of an E-Beam Prober is the Schlumberger IDS 5000, discussed in greater detail below.
e. Focussed Ion Beam for "micro-surgery" of VLSI circuits involves milling through passivation (or other layers) to uncover a submerged trace or test point and cutting a trace to isolate circuitry, as described, e.g., in Failure Analysis Using Focused Ion Beams, Test & Measurement World, November 1990, pp. 97-102.
f. Ultraviolet Non-contact Voltage Probing utilizes a photoelectric effect for making voltage measurements on conductor lines. Both DC voltage and AC waveform measurements can be made to submicron dimensions, as described, e.g., in Ultraprobe Brochure, Ultraprobe, Laguna Hills, Calif.
Returning our attention to the design phase, modern ECAD (Electronic Computer-Aided Design) systems facilitate the design of electronic circuits by providing a user with a set of software tools running on a digital computer. These software tools generally include a schematic editor, a schematic compiler, and a simulator, and numerous examples are available to the test engineer.
The schematic editor tool is pivotal to the operation of an ECAD system. By using this tool, a circuit designer can create and edit complex circuits, using both previously-created (stored) circuit descriptions and specially-created circuit descriptions, and interconnecting same. The display is conveniently in the form of a schematic diagram. Usually, a netlist or other numerical representation of the circuit is derived, typically by a compiler tool in the ECAD system, and the circuit design can be simulated with a simulator tool, also resident in the ECAD system. When the designer is satisfied that the circuit design is valid, a layout tool is invoked to produce yet another numerical representation of the circuit for use by fabrication equipment to create a physical device. Commonly, the various representations of the circuit are available interactively to the designer, who can switch from a schematic view, to a netlist, to a layout view.
The simulation phase of design is especially important, for if the design does not work at this stage, it certainly will not perform on a physical device. In order to simulate a circuit, the designer prepares a comprehensive list of input stimuli representing real input values to be applied to the simulation model of the circuit. The digital representation of the circuit is then compiled by a schematic compiler and translated into a form which is best suited to simulation. This new, translated representation of the circuit is then acted upon by a simulator, which produces numerical output analogous to the response of a real circuit with the same inputs applied. This output is then usually presented to the user in a graphical fashion. By viewing the simulation results, the user may then determine if the represented circuit will perform correctly when it is constructed. If not, he may then re-edit the schematic of the circuit using the schematic editor, re-compile and re-simulate. This process is performed iteratively until the user is satisfied that the design of the circuit is correct.
The Modular Design Environment ("MDE") produced by LSI Logic Corporation of Milpitas, Calif., is a suite of software tools for computers running the UNIX operating system produced by AT&T Corporation. For purposes of this discussion, MDE (resident in an appropriate workstation) shall be considered an ECAD system.
MDE comprises a schematic editor (LSED) and a simulator (LDS), among other software programs, and provides an example of commercially available tools of the aforementioned type. Another example of a schematic editor, schematic compiler, and schematic simulator may be found in the SCALDstation produced by Valid Logic Systems, Inc. of Mountain View, Calif.
After the design and simulation process is completed, to the designer's satisfaction, a physical device will be created. As noted above, this process is greatly facilitated a layout tool in the ECAD system. Masks are produced, based on the layout data, and the device is fabricated on photolithography equipment (e.g.).
After a physical device is created, it must be tested to verify its functionality. Various stand-alone testers are capable of applying a comprehensive set of test vectors (signals) to the inputs of the device, and logging (recording) signals at the outputs of the device. First, however, the test vectors must be generated, and these may be derived from the ECAD system's simulation stimuli. When, however, a fault is indicated, the tester can only provide "gross" information about the manifestation of the fault as indicated by a faulty voltage level on an output pin. In order to identify the source of the fault, it is necessary to trace the fault back from the output pin, generating a "fault tree" of candidate gates, nets, and the like, (i.e., "circuit elements") that are malfunctioning, and physically examine the condition of each of these candidate sources of error.
Examples of logic testers are found in the following patents and publications, incorporated by reference herein: U.S. Pat. Nos. 4,928,278, 4,726,025 and 4,705,970 and Application Note, "Automated Digital Signal Processing" (Massachusetts Computer corporation, 080-00976-00 0887-976).
In order to probe individual gates, or parts of gates, such as particular diffusion areas, vias, contacts, polysilicon structures, metallization layers, and the like, a probe tool having extremely fine resolution is required. Physical probing tools are somewhat effective, but tend to damage the device. Non-contacting probes, such as an electron beam (e-beam) prober, offer positional resolution on the order of 0.2 .mu.m, and are non-destructive.
One example of an E-Beam prober is the IDS 5000 E-Beam Prober, available from Schlumberger Technologies. The IDS 5000 is able to measure the state at precise locations (e.g., individual nets) on a device-under test ("DUT"). In the IDS 5000, an electron optical system produces a focused electron beam small enough to probe the most advanced device geometries (e.g., down to 0.3 microns). The following "tools" are also included in the IDS 5000:
An interactive positioning tool is provided for positioning the e-beam probe.
A Scope Tool is provided for displaying "live" waveforms at selected positions on the device, as detected by the e-beam probe.
A "navigational" tool is provided, which can be loaded with schematic, netlist, and layout representations of the DUT, to facilitate backtracking from one level of representation to another, without manual signal tracing.
A Scanning Electron Microscope (SEM) Tool provides a voltage-contrast image of the DUT in real time, and shows the logic states of different nets.
A pointer in the SEM or layout displays can be moved interactively, and the signal detected by the probe at a corresponding point on the DUT is continuously displayed in the Scope Tool.
A Layout Tool allows the user to "browse" through the downloaded physical layout of the DUT and locate a particular signal without referring to hard-copy plots. The Layout Tool has a notion of hierarchy, and sub-cells can be exploded.
A Schematic Tool graphically displays the downloaded schematic of the DUT, which is transferred to the IDS from outside the system. With this tool, the user is able to "browse" through the design, and links to the Layout Tool allow selection of a net in the schematic and corresponding net in the Layout Tool. A netlist text file can also be downloaded and displayed, and used in a similar manner.
DUTs can be tested by connecting to a tester, and increasing clock speeds until a DUT starts to fail, and comparing signal measurements at the various clock speeds. A Dynamic Fault Imaging Application Tool can acquire a sequence of stroboscopic measurements from a known good device and compare these images with a similar sequence from a device-under-test (DUT).
Equipment such as the IDS 5000 has enormous capability to measure signal levels at precise locations on a DUT, thereby allowing for precise analysis of suspect failing circuit elements, and also has a reasonably friendly user interface to allow interactive positioning of the e-beam probe, once schematics and layouts (and netlists) are loaded. Nevertheless, an element-by-element analysis, employing a comprehensive set of test vectors is time consuming.
On the other hand, leakage detection techniques such as Liquid Crystal and Photo-Emission (described above) provide only the sites showing leakages of where a fault is occurring, but in this sense these techniques are faster.
ECAD systems have no inherent ability to test a physical device.
What is needed is a technique for quickly pinpointing faults in a device, and such is disclosed herein.